In this work an integrated multi-order digital control unit (DCU), for the generation of a maximum length sequence (MLS) circulant matrix, is proposed. The system provides the binary MLS through serial output. It has the possibility to select the M order of the MLS according to the application. When compared to conventional implementations, the proposed system does not rely on read-only memory (ROM) data storage since the circulant sequences are generated on the fly during the circuit's operation. This permits to implement multiple order circulant matrices, while mantaining a reduced area occupation. Moreover, the proposed circuit can be implemented with digital standard cell synthesis, avoiding dedicated digital flows for memories. The DCU has been verified with behavioral simulation using a 2MHz clock frequency and has been realized in CMOS 28 nm FDSOI technology with a total area occupation of 45 µ m × 45 µ m. From the RTL synthesis, a total power consumption of 8.2 µ W is obtained.
An Integrated Multi-Order Digital Control Unit for Maximum Length Sequence Circulant Matrix Generation
Radogna A. V.
Primo
;D'Amico S.Ultimo
2022-01-01
Abstract
In this work an integrated multi-order digital control unit (DCU), for the generation of a maximum length sequence (MLS) circulant matrix, is proposed. The system provides the binary MLS through serial output. It has the possibility to select the M order of the MLS according to the application. When compared to conventional implementations, the proposed system does not rely on read-only memory (ROM) data storage since the circulant sequences are generated on the fly during the circuit's operation. This permits to implement multiple order circulant matrices, while mantaining a reduced area occupation. Moreover, the proposed circuit can be implemented with digital standard cell synthesis, avoiding dedicated digital flows for memories. The DCU has been verified with behavioral simulation using a 2MHz clock frequency and has been realized in CMOS 28 nm FDSOI technology with a total area occupation of 45 µ m × 45 µ m. From the RTL synthesis, a total power consumption of 8.2 µ W is obtained.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
